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NXP Semiconductors /MIMXRT1052 /SEMC /INTEN

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Interpret as INTEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IPCMDDONEEN)IPCMDDONEEN 0 (IPCMDERREN)IPCMDERREN 0 (AXICMDERREN)AXICMDERREN 0 (AXIBUSERREN)AXIBUSERREN 0 (NDPAGEENDEN_0)NDPAGEENDEN 0 (NDNOPENDEN_0)NDNOPENDEN

NDPAGEENDEN=NDPAGEENDEN_0, NDNOPENDEN=NDNOPENDEN_0

Description

Interrupt Enable Register

Fields

IPCMDDONEEN

IP command done interrupt enable
IPCMDERREN

IP command error interrupt enable
AXICMDERREN

AXI command error interrupt enable
AXIBUSERREN

AXI bus error interrupt enable
NDPAGEENDEN

This bit enable/disable the NDPAGEEND interrupt generation.

0 (NDPAGEENDEN_0): Disable

1 (NDPAGEENDEN_1): Enable
NDNOPENDEN

This bit enable/disable the NDNOPEND interrupt generation.

0 (NDNOPENDEN_0): Disable

1 (NDNOPENDEN_1): Enable

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data